Several problems, such as short channel effects and drain induced barrier lowering (DIBL) effects, can occur when transistor size is decreased. For example, if the channel width of the transistor is reduced to less than 50 nm, distribution of device characteristics may increase, and if the channel width is reduced to less than 30 nm, short channel effects and DIBL effects may occur, thereby hindering normal operation of the transistor.
In order to overcome these problems, studies on dual gate transistors have increased. Some dual gate transistors can include a channel with a thickness of less than 30 nm and a gate that is positioned either surrounding the channel or at both sides thereof. A conventional transistor can have a single gate electrode formed only on top of the channel structure, such that the electric field created by the gate voltage is anisotropically applied to the channel. Thus, the transistor may not be effectively controlled by the gate electrode, which may cause short channel effects.
In contrast, dual gate transistors may have gate electrodes formed on both sides of a thin channel, thereby allowing every portion of the channel region to be controlled by the gate electrode. Accordingly, current between the source and drain can be lowered when the transistor is off, power dissipation can be reduced, and on/off operations of the transistor can be effectively controlled.
A dual gate transistor formed in silicon on insulator (SOI) can prevent formation of parasitic transistors and can be easily used in conventional methods of forming transistors. Fin-FETs with a fin and a gate electrode are discussed in “2002 Symposium on VLSI Technology Digest of Technical Paper” by Fu-Liang Yang et al. As discussed in Yang, the fin is formed on an insulating layer of SOI substrate and the gate electrode is positioned over the fin. A double gate transistor with upper and lower gates and a parallel channel pattern is discussed in “Implementation and Characterization of Self-Aligned Double-Gate TFT with Thin Channel and Thick Source/Drain” by Shengdong Zhang et al., “IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, No. 5, MAY 2002”. In Zhang, the upper and lower gates are self-aligned to an insulating layer and the parallel channel pattern is interposed between the lower and upper gates. Dual gate transistors are also discussed in, for example, “A Spacer Patterning Technology for Nanoscale CMOS” by Yang-Kyu Chio, “IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, No. 3, MARCH 2002”. However, the transistors discussed in the above references are formed on SOI substrate, which can contribute to several problems, such as floating body effect, inferior thermal conductivity, expensive wafer price, and high defect density of the SOI substrate.
A dual gate transistor formed on a bulk silicon substrate (instead of the SOI substrate) is discussed in U.S. Pat. No. 6,355,532, “SUBTRACTIVE OXIDATION METHOD OF FABRICATING A SHORT-LENGTH AND VERTICALLY-ORIENTED CHANNEL, DUAL-GATE, CMOS FET” by John J. Seliskar et al. According to Seliskar, impurities can be implanted in the substrate between the channel segments during formation of the source and drain regions.
FIG. 1 is a cross-sectional view showing a conventional dual gate transistor formed on a bulk silicon substrate.
Referring to FIG. 1, a field oxide layer 20 is formed on the semiconductor substrate 10, and the substrate defined by the field oxide layer 20 is etched to form vertically protruding channel segments 12 that are laterally separated from one another. A gate electrode 14 is formed over the channel segments 12, and a gate oxide layer is formed between the gate electrode 14 and the channel segments 12.
FIG. 2 is a perspective view showing a portion of a conventional dual gate transistor formed on a bulk silicon substrate.
Referring to FIG. 2, a gate electrode 14 is positioned over the vertically protruding channel segments 12. Impurities are implanted into the silicon substrate at both sides of the gate electrode 14 to form source and drain regions (S/D), respectively. As discussed above, conventional vertical channel transistors can have source and drain regions formed not only in the channel segments 12, but also in the substrate adjacent to the channel segments 16. The channel segments 12 are surrounded by the gate electrode 14, such that full depletion or fill inversion can occur where the channel length is short. However, intrinsic transistors 15 may be formed in the substrate adjacent to the protruding channel segments 12 and may possibly cause DIBL effects, which can be typical in transistors with parallel channels.
FIG. 3 is a perspective view showing a conventional vertical channel transistor formed in SOI substrate.
Referring to FIG. 3, the transistor includes a SOI layer 24 with a plurality of parallel fins 30 formed on a buried oxide layer 22, a mask oxide layer 26 formed on the SOI layer 24, and a gate electrode 28 positioned over the mask oxide layer 26 and the fins 30. The gate electrode 28 includes a polysilicon layer 28a under the gate electrode and a low resistance layer 28b on the polysilicon layer 28a. The transistor is formed on the buried oxide layer 22 and is separated from the substrate, which can cause low thermal conductivity and floating body effects.